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1 rev. 1.0 february 1998 mosel vitelic msu2052/u2032 features postfix bla nk p j q u pa ck ag e dice 40l pdip 44l plcc 44l pqfp 44l lqfp pin/pad con fi g ura t io n page 18 pa ge 2 pa ge 2 pa ge 2 pa ge 2 di me ns i on page 18 page 14 page 15 page 16 page 17 l ogo siz e at t op ma r ki ng - 5.0 x 4.2 mm 4.5 x 3.8 mm 2.8 x 2.4 mm 2.8 x 2.4 mm m.v.i. w.b. philips l.g. in te l ccl. itri atmel msu2052 w78c52 80c52 gms80c502 80c52 cic80520 at 8 0 c 5 2 msu2032 w78c32 80c32 gms80c302 80c32 - - - - - at 8 0 c 3 2 cross reference specifications subject to change without notice, contact your sales representatives for the most recent information. working voltage : l series at 2.7v through 4.5v while s & c series at 4.5 v through 5.5 v general 80c51 family compatible 64 k byte external memory space 8 k byte rom 256 byte data ram three 16 bit timers/counters four 8-bit i/o ports full duplex serial channel bit operation instructions page free jumps 8 - bit unsigned division 8 - bit unsigned multiply bcd arithmatic direct addressing indirect addressing nested interrupt two priority level interrupt a serial i/o port power save modes: idle mode and power down mode working at 16/25/40 mhz clock description the mvi msu2052 series product is an 8 - bit single chip microcontroller. it provides hardware features and a powerful instruction set, neces- sary to make it a versatile and cost effective controller for those applications demand up to 32 i/o pins or need up to 64 k byte external memory either for program or for data or mixed. a serial input / output port is provided for i/o expansion, inter - processor communications, and full duplex uart. ordering information msu2032ihhk msu2052ihh - yyyk i: process identier {l, c}. hh: working clock in mhz {16, 25, 40}. yyy: production code {001, ..., 999} k: package type postx {as below table}. product list msu2032l16 , low working voltage 16 mhz rom less mcu msu2032c16 , 16 mhz rom less mcu msu2032c25 , 25 mhz rom less mcu msu2032c40 , 40 mhz rom less mcu msu2052l16 , low working voltage 16 mhz 4 kb internal rom mcu msu2052c16 , 16 mhz 4 kb internal rom mcu msu2052c25 , 25 mhz 4 kb internal rom mcu msu2052c40 , 40 mhz 4 kb internal rom mcu
2 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 t2ex/p1.0 t2/p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 res rxd/p3.0 txd/p3.1 #int0/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 #wr/p3.6 #rd/p3.7 xtal2 xtal1 vss vdd ad0/p0.0 ad1/p0.1 ad2/p0.2 ad3/p0.3 ad4/p0.4 ad5/p0.5 ad6/p0.6 ad7/p0.7 #ea ale #psen a15/p2.7 a14/p2.6 a13/p2.5 a12/p2.4 a11/p2.3 a10/p2.2 a9/p2.1 a8/p2.0 msu2032ihhp, msu2052ihh- yyyp (top view) 40l pdip msu2032ihhq, msu2052ihh- yyyq 44l pqfp (top view) ad4/p 0.4 ad5/p 0.5 ad6/p 0.6 ad7/p 0.7 #ea nc ale #psen a15/p 2.7 a14/p 2.6 a13/p 2.5 p 1.5 p 1.6 p 1.7 res rxd/p 3.0 nc txd/p 3.1 #int0/p 3.2 #int1/p 3.3 t0/p 3.4 t1/p 3.5 p 1.4 p 1.3 p 1.2 t2ex/p 1.1 t2/p 1.0 nc vdd ad0/p 0.0 ad1/p 0.1 ad2/p 0.2 ad3/p 0.3 #wr/p 3.6 #rd/p 3.7 xtal2 xtal1 vss nc a8/p 2.0 a9/p 2.1 a10/p 2.2 a11/p 2.3 a12/p 2.4 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 41 40 39 38 37 34 msu2032ihhu, msu2052ihh- yyyu 44l lqfp (top view) ad4/p 0.4 ad5/p 0.5 ad6/p 0.6 ad7/p 0.7 #ea nc ale #psen a15/p 2.7 a14/p 2.6 a13/p 2.5 p 1.5 p 1.6 p 1.7 res rxd/p 3.0 nc txd/p 3.1 #int0/p 3.2 #int1/p 3.3 t0/p 3.4 t1/p 3.5 p 1.4 p 1.3 p 1.2 t2ex/p 1.1 t2/p 1.0 nc vdd ad0/p 0.0 ad1/p 0.1 ad2/p 0.2 ad3/p 0.3 #wr/p 3.6 #rd/p 3.7 xtal2 xtal1 vss nc a8/p 2.0 a9/p 2.1 a10/p 2.2 a11/p 2.3 a12/p 2.4 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 41 40 39 38 37 34 msu2032ihhj, msu2052ihh- yyyj 44l plcc (top view) ad4/p 0.4 ad5/p 0.5 ad6/p 0.6 ad7/p 0.7 #ea nc ale #psen a15/p 2.7 a14/p 2.6 a13/p 2.5 p 1.5 p 1.6 p 1.7 res rxd/p 3.0 nc txd/p 3.1 #int0/p 3.2 #int1/p 3.3 t0/p 3.4 t1/p 3.5 p 1.4 p 1.3 p 1.2 t2ex/p 1.1 t2/p 1.0 nc vdd ad0/p 0.0 ad1/p 0.1 ad2/p 0.2 ad3/p 0.3 #wr/p 3.6 #rd/p 3.7 xtal2 xtal1 vss nc a8/p 2.0 a9/p 2.1 a10/p 2.2 a11/p 2.3 a12/p 2.4 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 pin configurations
3 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 block diagram res vdd vss xtal2 xtal1 #ea #psen ale timer 1 timer 0 decoder & register 256 bytes ram 8k bytes rom register program counter pc increamenter buffer dptr stack pointer port 3 latch port 1 latch port 2 latch port 0 latch port 0 driver port 2 driver port 1 driver port 3 driver 8 8 8 8 reset circuit power circuit interrupt circuit timming generator to pertinent blocks to whole chip to pertinent blocks to whole system acc buffer1 buffer2 alu psw instruction register timer 2
4 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 40 pdip pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 dice pad# 39 40 41 42 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15~17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37,38 44 plcc pin# 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 symbol t2ex/p1.0 t2/p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 res rxd/p3.0 txd/p3.1 #int0/p3.2 #int1/p3.3 t0/p3.4 t1/p3.5 #wr/p3.6 #rd/p3.7 xtal2 xtal1 vss a8/p2.0 a9/p2.1 a10/p2.2 a11/p2.3 a12/p2.4 a13/p2.5 a14/p2.6 a15/p2.7 #psen ale #ea ad7/p0.7 ad6/p0.6 ad5/p0.5 ad4/p0.4 ad3/p0.3 ad2/p0.2 ad1/p0.1 ad0/p0.0 vdd active l/- l/- l/- l/- l h l i/o i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o o i i/o i/o i/o i/o i/o i/o i/o i/o o o i i/o i/o i/o i/o i/o i/o i/o i/o names bit 0 of port 1 & timer 2 bit 1 of port 1 & timer control bit 2 of port 1 bit 3 of port 1 bit 4 of port 1 bit 5 of port 1 bit 6 of port 1 bit 7 of port 1 reset bit 0 of port 3 & receive data bit 1 of port 3 & transmit data bit 2 of port 3 & low true interrupt 0 bit 3 of port 3 & low true interrupt 1 bit 4 of port 3 & timer 0 bit 5 of port 3 & timer 1 bit 6 of port 3 & write (low enable) bit 7 of port 3 & read (low enable) crystal out crystal in sink voltage, ground bit 0 of port 2 & address 8 bit 1 of port 2 & address 9 bit 2 of port 2 & address 10 bit 3 of port 2 & address 11 bit 4 of port 2 & address 12 bit 5 of port 2 & address 13 bit 6 of port 2 & address 14 bit 7 of port 2 & address 15 program store enable (low enable) address latch enable external access first 8 kb memory bit 7 of port 0 & address or data 7 bit 6 of port 0 & address or data 6 bit 5 of port 0 & address or data 5 bit 4 of port 0 & address or data 4 bit 3 of port 0 & address or data 3 bit 2 of port 0 & address or data 2 bit 1 of port 0 & address or data 1 bit 0 of port 0 & address or data 0 drive voltage, +3 vcc (or +5 vcc) 44 lqfp pin# 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 44 pqfp pin# 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 pin descriptions
5 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 pin descriptions vss circuit ground potential. vdd +3v (or +5 v) power supply during operation. port 0 port 0 is an 8-bit open drain bidirectional i/o port. it is also the multiplexed low-order address and data bus when using external memory. it also contains the timer 2 & its control pins. port 1 port 1 is an 8-bit quasi-bidirectional i/o port with internal pull-up resistance. port 2 port 2 is an 8-bit quasi-bidirectional i/o port with internal pull-up resistance. it also emit the high-order address byte when accessing external memory. port 3 port 3 is an 8-bit quasi-bidirectinal i/o port with internal pull-up resistance. it also contains the interrupt, timer, serial port and #rd as well as #wr pins that are used by various options. the output latch corresponding to a secondary function must be programmed to one (1) for that function to operate. the secondary functions are assigned to the pins of port 3, as follows: - rxd/data (p3.0). serial port's transmitter data output (asynchronous) or data input/output (asynchronous). - txd/clock (p3.1). serial port's transmitter data output (asynchronous) or data output (asynchronous). - #int0 (p3.2). interrupt 0 input or gate control input for counter 0. - #int1 (p3.3). interrupt 1 input or gate control input for counter 1. - t0 (p3.4). input to counter 0. - t1 (p3.4). input to counter 1. - #wr (p3.6). the write control signal latches the data byte from port 0 into the external data memory. - #rd (p3.7). the read control signal enables external data memory to port 0. res a high on this pin for two machine cycles (24 clocks) while the oscillator is running, resets the device. the data in ram is preserved when reset signals - reset does not clear the data in ram. ale provides address latch enable output used for latching the address into external memory during normal operation. #psen the program store enable output is a control signal that enables the external program memory to the bus during normal fetch operations. #ea when held at a ttl high level, the msu2052 executes instructions from the internal rom when the pc is less than 4096. when held at a ttl low level, the msu2052 fetches all instuctions from external program memory. xtal 1 input to the oscillator's high gain amplifier. a crystal or external source can be used. xtal 2 output from the oscillator's amplifier. required when a crystal is used. terms idle mode during idle mode, the cpu is stopped but below blocks are kept functioning: clock generator, ram, timer/ counters, serial port and interrupt block. to save power consumption, user's software program can invoke this mode. the on-chip data ram retains the values during this mode, but the processor stops executing instructions. in idle mode (idl=1), the oscillator continues to run and the interrput, and timer blocks continue to be clocked but the clock signal is gated off to the cpu. the activities of the cpu no longer exist unless waiting for an interrupt request. -an instruction that sets flag (pcon.0) causes that to be the last instruction executed before going into the idle mode. -in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer function. -the cpu status is entirely preserved in its: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. -there are three ways to terminate the idle mode. 1) by interrupt activation of any enabled interrupt will cause flag (pcon.0) to be cleared by hardware, termination the idle mode. after the program wakes up, the pc value will point as interrupt vector (if enable ie register) and execute interrupt service routine then return to pc+1 address after the program wakes up. 2) by hardware reset since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. all sfr and pc value will be cleared to reset value. 3) by one of clk, data, port 2.0-2.7 transition to low (falling edge trigger) after the program wakes up, the pc value will be 0023h (if enable ie register) and execute interrupt service routine and then returns to pc+1 address after the program wakes up.
6 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 power down mode it saves the ram content, stops the clock generator and disables every other blocks' function until the coming hardware reset. to save even more power consumption, user's software program can invoke this mode. the sfrs and the on-chip data ram retain their values during this mode, but the porcessor stops executing instructions. in power-down mode (pd=1) the oscillator is frozen. -an instruction that sets flag (pcon.1) causes that to be the last instruction executed before going into the power down mode. -in the power down mode, the on-chip oscillator is stopped. with the clock frozen, all functions are stopped, but the on-chip ram and special function registers are held. -reset redefines all the sfrs, but does not change the on-chip ram. -there are two ways to terminate the power down mode. 1) by hardware reset all sfr and pc value will be cleared to reset value. 2) one of clk, data, port 2.0-2.7 transition to low (falling edge trigger) after the program wakes up, the pc value will be 0023h (if enable ie register) and execute interrupt service routine and then returns to pc+1 address after the program wakes up. -care must be taken, however, to ensure that vcc is not reduced before the power down mode is invoked, and that vcc is restored to its normal operating level before the power down mode is terminated. -the hardware reset must be held active long enough to allow the oscillator to restart and stabilize. general of above user should fix the attention on using wake up from port 2: -the user should write the power down or idle mode flag value to one ram address before write pcon to distinguish waking up from power down mode or idle mode. -after idle mode or power down mode wakes up, the interrupt service routine will be executed first and then executes pc+1 address if the ie register is enabled before entering power down mode or idle mode. the interrupt service routine will not be executed but cpu executes pc+1 address program if disable ie register. -after wake up power down or idle mode the idf flag will be set by hardware. the idf flag be cleared at the isr execution time. if ie register is disable, the idf flag will not be cleared when power down or idle mode wakes up. mode program memory ale #psen port 0 port 1 port 2 port 3 idle idle power down power down internal external internal external 1 1 0 0 1 1 0 0 data float data float data data data data data address data data data data data data the state of pins during idle and power-down mode symbol v dd - vss v in v out t (operating) t (storage) name dc supply voltage input voltage output voltage operating temperature storage temperature rating -0.5 ~ +5.0 -0.5 ~ +7.0 vss-0.3 ~ v dd +0.3 vss ~ v dd 0 ~ +70 -55 ~ +125 unit v v v absolute maximal rating * note: operation beyond absolute maximal rating can adversely affect device reliability. c c remark u20x1l u20x1s,u20x1c
7 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 ac characteristics (16/25/40 mhz, operating conditions; cl for port 0, ale and psen outputs=150pf; cl for all other outputs=80pf) symbol t lhll t avll t llax t lliv t llpl t plph t pliv t pxix t pxiz t aviv t plaz t rlrh t wlwh t rldv t rhdx t rhdz t lldv t avdv t llyl t avyl t qvwh t qvwx t whqx t rlaz t yhlh t chcl t clcx t clch t chcx t, t clcl parameter ale pulse width address valid to ale low address hold after ale low ale low to valid instruction in ale low to #psen low #psen pulse width #psen low to valid instruction in instruction hold after #psen instruction float after #psen address to valid instruction in #psen low to address float #rd pulse width #wr pulse width #rd low to valid data in data hold after #rd data float after #rd ale low to valid data in address to valid data in ale low to #wr or #rd low address valid to #wr or #rd low data valid to #wr high data valid to #wr transition data hold after #wr #rd low to address float #wr or #rd high to ale high clock fall time clock low time clock rise time clock high time clock period valid cycle rd/wrt rd/wrt rd/wrt rd rd rd rd rd rd rd rd rd wrt rd rd rd rd rd rd/wrt rd/wrt wrt wrt wrt rd rd/wrt min. 115 43 53 53 173 0 365 365 0 178 230 403 38 73 53 typ. max 240 177 87 292 10 302 145 490 542 197 72 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns remarks operating conditions symbol t a v cc3 v cc5 f osc 16 f osc 25 f osc 40 description ambient temperature under bias supply voltage oscillator frequency min. 0 2.7 4.5 3.0 16 25 max. 70 4.5 5.5 16 25 40 unit v v mhz mhz mhz remarks u20x2l u20x2c u20x2i16 u20x2i25 u20x2i40 c typ. 25 3.0 5.0 16 25 40 f osc 16 2xt - 10 t - 20 t - 10 t - 10 3xt - 15 0 6xt - 10 6xt - 10 0 3xt - 10 4xt - 20 7xt - 35 t - 25 t + 10 t - 10 4xt - 10 3xt - 10 t + 25 5xt - 20 10 5xt - 10 2xt + 20 8xt - 10 9xt - 20 3xt + 10 5 t + 10 variable f osc min. max. 1/ fosc typ. 63
8 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 dc characteristics (16/25/40 mhz, typical operating conditons, valid for u20x2c series) symbol v ilx v ile v ilr v ihx v ihe v ihr v ola v ol0 v ol1 v oha v oh0 v oh1 v oh2 i ol0 i il i ih i tl i li r res r x c io i cc parameter input low voltage " " input high voltage " " output low voltage " " output high voltage " " " " " " " output low current logical 0 input current logical 1 input current logic transition current input leakage current reset pulldown resistance crystal feedback resistance pin capacitance power supply current valid xtal1 #ea res xtal1 #ea res ale, #psen ports 0,3 ports 1,2 ale, #psen port 0 ports 1,3 port 2 ports 0,3 ports 1,2,3 port 0 ports 1,2,3 port 0 res xtal1,2 vdd vdd vdd min. typ. max unit v v v v v v mv mv mv v v v v v v v v ma ua ua ua ua kohm kohm pf ma ma ua test conditions i ol = 3.2 ma i ol = 3.2 ma i ol = 1.6 ma i oh = -60 ua i oh = -10 ua i oh = -800 ua i oh = -80 ua i oh = -60 ua i oh = -10 ua i oh = -60 ua i oh = -10 ua v ol = 0.45v, note 1 v in = 0.45 v v in = 5.0 v v in = 2.0 v 0.45v < vin < vcc freq=1mhz, ta=25 ? active mode, 16 mhz idle mode, 16mhz power down mode -0.5 0 -0.5 70%vcc 20%vcc+0.9 70%vcc 2.4 90%vcc 2.4 90%vcc 2.4 90%vcc 2.4 90%vcc 50 90 18 5 3 10 20%vcc-0.1 20%vcc-0.3 20%vcc-0.1 vcc+0.5 vcc+0.5 vcc+0.5 450 450 450 -50 1.5 -650 10 150 330 10 8 5 45 note 1 : no more than 80 ma i ols for all 16-bit ports 0 & 3 output pins.
9 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 dc characteristics (16 mhz, typical operating conditons, valid for u20x2l series) symbol v ilx v ile v ilr v ihx v ihe v ihr v ola v ol0 v ol1 v oha v oh0 v oh1 v oh2 i il i ih i tl i li r res r x c io i cc parameter input low voltage " " input high voltage " " output low voltage " " output high voltage " " " " " " " logical 0 input current logical 1 input current logic transition current input leakage current reset pulldown resistance crystal feedback resistance pin capacitance power supply current valid xtal1 #ea res xtal1 #ea res ale, #psen ports 0,3 ports 1,2 ale, #psen port 0 ports 1,3 port 2 ports 1,2,3 port 0 ports 1,2,3 port 0 res xtal1,2 vdd vdd vdd min. typ. max unit mv mv mv v v v mv mv mv v v v v v v v v ua ua ua ua kohm kohm pf ma ma ua test conditions i ol = 3.2 ma i ol = 3.2 ma i ol = 1.6 ma i oh = -60 ua i oh = -10 ua i oh = -800 ua i oh = -80 ua i oh = -60 ua i oh = -10 ua i oh = -60 ua i oh = -10 ua v in = 0.45 v v in = 3.0 v v in = 1.4 v 0.45v < vin < vcc freq=1mhz, ta=25 ? active mode, 16 mhz idle mode, 16mhz power down mode 1.8 2.4 2.2 2.4 1.8 2.4 1.8 2.4 50 90 2 1 10 vcc+0.3 vcc+0.3 vcc+0.3 400 400 400 45 1 250 8 150 330 10 7 4.5 45
10 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 data memory read cycle timing program memory read cycle timing t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 osc ale #psen #rd, #wr port2 port0 address a - a 15 8 address a -a 15 8 1 2 5 7 3 3 4 6 8 float float a -a float float float 7 0 inst in a -a 7 0 inst in t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 osc ale #psen #rd port2 port0 address a - a 15 8 1 2 5 7 3 3 4 6 8 float float a -a float 7 0 inst in data in t3 address or flloat
11 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 data memory write cycle timing t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 osc ale #psen #wr port2 port0 address a - a 15 8 1 5 6 2 2 3 4 float a -a 7 0 data out t3 address or float inst x1 inputs p0, p1 inputs p2, p3 output by mov px,src rxd at serial port shift clock (mode 0) sampled sampled current data next data sampled t7 t8 t9 t10 t11 t12 t1 t2 t3 t4 t5 t6 t7 t8 t6 i/o ports timing
12 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 t avdv t avll t llax t avyl t rlaz t rldv t rhdx t rhdz t yhlh t llyl t rlrh t lldv p2.0-p2.7 or a8-a15 from dph a0-a7 from ri or data in a0-a7 from instr. in a8-a15 from pch port 2 port 0 #rd ale #psen tm.i external program memory read cycle tm.ii external data memory read cycle #psen ale port 0 port 2 a8 - a15 a8 - a15 a0 - a7 instruction. in a0 - a7 t aviv t lliv t avll t llax t plaz t pliv t llpl t lhll t pxiz t pxix t plph timing critical, requirement of external clock (vss=0.0v is assumed) t clcl t chcl t clcx t clch t chcx vdd-0.5v 0.45v 70%vdd 20%vdd-0.1v
13 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 t avll t llax t avyl t yhlh t llyl t wlwh p2.0-p2.7 or a8-a15 from dph a0-a7 from ri or dpl data out a0-a7 from pcl instr. in a8-a15 from pch port 2 port 0 #wr ale #psen tm.iii external data memory write cycle t qvwx t whqx t lhll x'tal c1 c2 r 3 mhz 15 pf 15 pf open 12 mhz 30 pf 30 pf open 16 mhz 30 pf 30 pf open x1 x2 msu2052 msu2032 x'tal r application reference c1 c2 t qvwh 6 mhz 15 pf 15 pf open x'tal c1 c2 r 12 mhz 30 pf 30 pf open 25 mhz 15 pf 15 pf 62 kohm 40 mhz 5 pf 5 pf 4.7 kohm 16 mhz 30 pf 30 pf open valid for u2052l16/ u2032l16 valid for u2052c16/ u2032c16/ u2052c25/ u2032c25/ u2052c40/ u2032c40
14 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 note: 1.dimension d max & s include mold flash or tie bar burrs. 2.dimension e1 does not include interlead flash. 3.dimenseion d & e1 include mold mismatch and are determined at the mold parting line. 4.dimension b1 does not include dambar protrusion/ infrusion. 5.controlling dimension is inch. 6.general appearance spec. should base on final visual inspection spec. 40l 600mil pdip information ? c ea e e1 d a1 s e1 b1 b a2 a l symbol a a1 a2 b b1 c d e e1 e1 l ? ea s dimension in inch minimal/maximal - / 0.210 0.010 / - 0.150 / 0.160 0.016 / 0.022 0.048 / 0.054 0.008 / 0.014 - / 2.070 0.590 / 0.610 0.540 / 0.552 0.090 / 0.110 0.120 / 0.140 0.630 / 0.670 dimension in mm minimal/maximal - / 5.33 0.25 / - 3.81 / 4.06 0.41 / 0.56 1.22 / 1.37 0.20 / 0.36 - / 52.58 14.99 / 15.49 13.72 / 14.02 2.29 / 2.79 3.05 / 3.56 16.00 / 17.02 - / 2.29 0 / 15 0 / 15 / 0.090
15 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 note: 1.dimension d & e does not include interlead flash. 2.dimension b1 does not include dambar protrusion/ intrusion. 3.controlling dimension:inch 4.general appreance spec. should base on final visual inspection spec. 44l plastic leaded chip carrier (plcc) 6 7 d h d e h e 0 e g d b1 b c g e l a2 a a1 y symbol a a1 a2 b1 b c d e e gd ge hd he l dimension in inch minimal/maximal - / 0.185 0.020 / - 0.145 / 0.155 0.026 / 0.032 0.016 / 0.022 0.008 / 0.014 0.648 / 0.658 0.648 / 0.658 0.050 bsc 0.590 / 0.630 0.590 / 0.630 0.680 / 0.700 0.680 / 0.700 0.090 / 0.110 - / 0.004 / dimension in mm minimal/maximal - / 4.70 0.51 / - 3.68 / 3.94 0.66 / 0.81 0.41 / 0.56 0.20 / 0.36 16.46 / 16.71 16.46 / 16.71 1.27bsc 14.99 / 16.00 14.99 / 16.00 17.27 / 17.78 17.27 / 17.78 2.29 / 2.79 - / 0.10 q y /
16 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 note: dimension d1 and e1 do not include mold protrustion. allowance protrusion is 0.25mm per side. dimensions d1 and e1 do include mold mismatch and are determined at datum plane. dimension b does not include dambar protrusion. allowance dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. e2 e1 e d2 d1 d q seating plane c a2 a1 a c l l1 s e b b r2 r1 q 3 q 2 44l plastic quad flat package 1. 2. 0 1 gage plane 0.25 mm symbol a a1 a2 b c d d1 d2 e e1 e2 e l l1 r1 r2 s dimension in inch minimal/maximal - / 0.100 0.006 / 0.014 0.071 / 0.087 0.012 / 0.018 0.004 / 0.009 0.520 bsc 0.394 bsc 0.315 0.520 bsc 0.394 bsc 0.315 0.031 bsc 0.029 / 0.041 0.063 0.005 / - 0.005 / 0.012 dimension in mm minimal/maximal - / 2.55 0.15 / 0.35 1.80 / 2.20 0.30 / 0.45 0.09 / 0.20 13.20 bsc 10.00 bsc 8.00 13.20 bsc 10.00 bsc 8.00 0.80 bsc 0.73 / 1.03 1.60 0.13 / - 0.13 / 0.30 0.20 / - as left as left as left as left q c q q q 1 2 3 0 / 7 0 / - 10 ref 7 ref 0.004 0.10 0.008 / -
17 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 note: dimension d1 and e1 do not include mold protrustion. allowance protrusion is 0.25mm per side. d1 and e1 are maximal plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowance dambar protrusion shall not cause the lead width to exceed the maximal b dimension by more than 0.08 mm. dambar can not be located on the lower radius or the foot. minimal space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 44l low profile quad flat package 1. 2. 3. e2 e1 e d2 d1 d q seating plane c a2 a1 a c l l1 s e b b r2 r1 q 3 q 2 0 1 gage plane 0.25 mm symbol a a1 a2 b c d d1 d2 e e1 e2 e l l1 r1 r2 s dimension in inch minimal/maximal - / 0.063 0.002 / 0.006 0.053 / 0.057 0.012 / 0.018 0.004 / 0.008 0.472 bsc 0.393 bsc 0.315 0.472 bsc 0.393 bsc 0.315 0.031 bsc 0.018 / 0.030 0.039 ref 0.003 / - 0.003 / 0.008 dimension in mm minimal/maximal - / 1.60 0.05 / 0.15 1.35 / 1.45 0.30 / 0.45 0.09 / 0.20 12.00 bsc 10.00 bsc 8.00 12.00 bsc 10.00 bsc 8.00 0.80 bsc 0.45 / 0.75 1.00 ref 0.08 / - 0.08 / 0.20 0.20 / - as left as left as left as left q c q q q 1 2 3 0 / 7 0 / - 11 /13 11 /13 0.004 0.10 0.008 / -
18 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 bonding information pid 252* 12/96 pid 252** 01/97 pid 252*** 02/97 pid 252a 02/98 index pad-name p1.5 p1.6 p1.7 res p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 xtal2 xtal1 vss vss vss p2.0 p2.1 p2.2 p2.3 p2.4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 index pad-name p2.5 p2.6 p2.7 #psen ale #ea p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 vdd vdd p1.0 p1.1 p1.2 p1.3 p1.4 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 x-coord y-coord 237 400 559 722 882 1044 1204 1366 1526 1688 1931 1931 1931 1931 1931 1931 1931 1931 1931 1931 1931 1931 x-coord 1688 1526 1366 1204 1044 882 722 559 400 237 168 168 168 168 168 168 168 168 168 168 168 186 186 186 186 186 186 186 186 186 186 310 537 769 1090 1291 1442 1593 1791 2016 2243 2468 2696 y-coord 2874 2874 2874 2874 2874 2874 2874 2874 2874 2874 2595 2367 2142 1915 1717 1566 1369 1144 917 692 464 1 2 3 4 5 6 7 8 9 10 32 31 30 29 28 27 26 25 24 23 11 12 13 14 15 16 17 18 19 20 21 22 43 42 41 40 39 38 37 36 35 34 33 msu2052/u2032 2200 x 3160 ( m m) pad size : 90 x 90 ( m m) substrate should be bonded to vss logo
19 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 to: mosel vitelic inc. 886-3-578-4732 (fax #) attn: sales & marketing department product request form we hereby request mvi to start producing msu2052 which is specified below. please send us the product code and a hardcopy of data code as well as data code file duplicated on floppy diskette. no further confirmation is necessary. production will start automatically once you receive our data code and verify that the checksum is match. mass production of the captioned device shall be done in accordance with the purchase order(s) issued by us or a company specified by us. all terms and conditions are based on the development agreement and/or contract signed between mvi and us. data code descriptions code length file length file name checksum unused data byte format media h 00h filled ffh filled hex format binary code format eprom 8751 chip file on floppy e-mail file top marking (fill only for packaged) ic descriptions dice form p type = 40l-pdip j type = 44l-plcc q type = 44l-pqfp l type = 44l-lqfp phone # : company name : signature : name (typed) : position title : department, section : signature date : fax # : date code location descriptions use mvi logo, date code and part number use my specifications as described below use regular date code as mvi's leave it as blank use right side five letters leave it blank use my specifications as attachment logo specifications part number specified, less than 15 digits specify below fields only for customer top marking u2052l16, 16 mhz low working voltage u2052c16, 16 mhz u2052c25, 25 mhz u2052c40, 40 mhz
20 re v . 1.0 f ebr uar y 1998 mosel vitelic msu2052/u2032 to: mosel vitelic inc. 886-3-578-4732 (fax#) attn: sales & marketing department logo top marking request & spec. we hereby request mvi to have our logo printed on top of the device package. below is the specification of our logo in 20:1 scale base. this logo diagram is clear enough and is able to be shrunk directly to fit into available top marking area described on page. phone # : company name : signature : name (typed) : position title : department, section : signature date : fax # :
mosel vitelic w orld wide offices msu2052/u2032 ?cop yr ight 1998, mosel vitelic inc. 1/98 pr inted in u .s .a. mosel vitelic 3910 n. first street, san jose , ca 95134-1501 ph: (408) 433-6000 f ax: (408) 433-0952 tlx: 371-9461 u .s. sales offices the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2665-4883 fax: 852-2664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-578-3344 fax: 886-3-579-2838 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 81-43-299-6000 fax: 81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel ) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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